The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Scaling down presents difficulties, especially with lithography system. For example, light diffraction in an optical lithography system becomes an obstacle for further scaling down a feature size. Charged particle beam lithography systems can be another alternative to scale down the feature size, but these systems often suffer from reduced throughput. Accordingly, what is needed is a method to increase wafer throughput in a lithography system, such as a charged particle beam lithography system.